A Meta Model Supporting both Hardware and Smalltalk-based Execution of FPGA Circuits

Abstract : High level synthesis (HLS) refers to an automated process that creates a digital hardware from an algorithmic description of some computation. From the perspective of Smalltalk, this process consists of converting code from the oriented object level to the register transfer level (RTL), that supports direct compilation to the hardware level. In this paper, we present first steps to achieve this process. We introduce a Smalltalk-based meta-model that allows expressing descriptions (i.e. models) of digital circuits. These descriptions can be materialized as Smalltalk code. A such circuit description can be run on top of the Smalltalk VM, simulating the parallelism intrinsic of hardware. Alternatively, it can be compiled into a binary representation directly transferable to FPGA chips, which can run and exchange data with Smalltalk objects.
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Xuan Sang Le, Loic Lagadec, Luc Fabresse, Jannik Laval, Noury Bouraqadi. A Meta Model Supporting both Hardware and Smalltalk-based Execution of FPGA Circuits. IWST 2015, ESUG, Jul 2015, Bressia, Italy. ⟨10.1145/2811237.2811296⟩. ⟨hal-01179466⟩



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