%0 Conference Proceedings
%T A Meta Model Supporting both Hardware and Smalltalk-based Execution of FPGA Circuits
%+ Centre for Digital Systems (CERI SN - IMT Nord Europe)
%+ Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC)
%A Le, Xuan Sang
%A Lagadec, Loic
%A Fabresse, Luc
%A Laval, Jannik
%A Bouraqadi, Noury
%Z Best paper award
%< avec comité de lecture
%( IWST '15: Proceedings of the International Workshop on Smalltalk Technologies
%B IWST 2015
%C Bressia, Italy
%8 2015-07-15
%D 2015
%R 10.1145/2811237.2811296
%K FPGA
%K Pharo
%K Smalltalk
%K Dynamic
%K VHDL
%K Meta-model
%Z Computer Science [cs]/Computation and Language [cs.CL]
%Z Computer Science [cs]/Programming Languages [cs.PL]Conference papers
%X High level synthesis (HLS) refers to an automated process that creates a digital hardware from an algorithmic description of some computation. From the perspective of Smalltalk, this process consists of converting code from the oriented object level to the register transfer level (RTL), that supports direct compilation to the hardware level. In this paper, we present first steps to achieve this process. We introduce a Smalltalk-based meta-model that allows expressing descriptions (i.e. models) of digital circuits. These descriptions can be materialized as Smalltalk code. A such circuit description can be run on top of the Smalltalk VM, simulating the parallelism intrinsic of hardware. Alternatively, it can be compiled into a binary representation directly transferable to FPGA chips, which can run and exchange data with Smalltalk objects.
%G English
%2 https://hal.univ-brest.fr/hal-01179466/document
%2 https://hal.univ-brest.fr/hal-01179466/file/IWST_2015_submission_6%20%281%29.pdf
%L hal-01179466
%U https://hal.univ-brest.fr/hal-01179466
%~ UNIV-BREST
%~ INSTITUT-TELECOM
%~ ENSTA-BRETAGNE
%~ CNRS
%~ UNIV-UBS
%~ ENSTA-BRETAGNE-STIC
%~ ENIB
%~ LAB-STICC
%~ INSTITUTS-TELECOM
%~ IMT-NORD-EUROPE
%~ CERI-SN