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Communication dans un congrès

A High-Level Programming Model to Ease Pipeline Parallelism Expression On Shared Memory Multicore Architectures

Nader Khammassi 1 Jean-Christophe Le Lann 2
1 Lab-STICC_ENSTB_CACS_MOCS ; IDM
STIC - Département STIC [Brest], Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
2 Lab-STICC_ENSTAB_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
Abstract : Pipeline execution pattern is a recurrent execution configuration in many application domains involving stream processing such as digital signal processing and data compression. Unfortunately, lowlevel parallel programming models exacerbate the difficulties of expressing pipeline parallelism and require verbose restructuring of the code and complex scheduling techniques to perform efficient execution on modern multicore architectures. High-level programming models are in high-demand as they reduce the burdens of programmers, ease parallelism expression and handle transparently tasks scheduling and communication. XPU[20] is a high-level programming model which aims to ease parallelism expression through exploiting meta-programming capabilities of standard C++. In this paper we focus on pipeline parallelism expression, we present the programming model which allows pipeline construction. We describe its internal design and the runtime implementation of the pipeline execution pattern and finally we show an example of image processing application implementing real-time adaptive edge detection algorithm. We reuse an existing sequential implementation to implement a pipelined version using both XPU and TBB. We compare the two versions in term of expressivity and performance. We note that XPU version performs about 20% faster than TBB on a 16-threads multicore platform and requires 80% less extra-code than TBB to express pipeline parallelism. Our experiments show that our programming model provides both programmability and execution efficiency.
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https://hal.archives-ouvertes.fr/hal-00989661
Contributeur : Annick Billon-Coat <>
Soumis le : lundi 12 mai 2014 - 11:22:42
Dernière modification le : vendredi 23 avril 2021 - 03:40:42

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  • HAL Id : hal-00989661, version 1

Citation

Nader Khammassi, Jean-Christophe Le Lann. A High-Level Programming Model to Ease Pipeline Parallelism Expression On Shared Memory Multicore Architectures. HPC 2014, Apr 2014, Tampa, FL, United States. pp.XX. ⟨hal-00989661⟩

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