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tel-01661569v1
Thèse
software/FPGA co-design for Edge-computing : Promoting object-oriented design Other [cs.OH]. Université de Bretagne occidentale - Brest, 2017. English. ⟨NNT : 2017BRES0041⟩ |
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hal-01006128v1
Communication dans un congrès
A Prototyping Platform for Virtual Reconfigurable Units RECOSOC 2014, May 2014, Montpellier, France |
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hal-01405860v1
Communication dans un congrès
ZeFF : Une plateforme pour l’intégration d’architectures overlay dans le Cloud COMPAS 2016, Jul 2016, Lorient, France |
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hal-02513256v1
Communication dans un congrès
Towards a Hardware DSL Ecosystem: RubyRTL and Friends OSDA'2020 Open Source Hardware Design, colocated with DATE'20, Mar 2020, Grenoble, France |
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hal-02123124v1
Communication dans un congrès
Constant Time Hardware Architecture for a Gaussian Smoothing Filter 2018 International Conference on Signal Processing and Information Security (ICSPIS), IEEE, Nov 2018, DUBAI, United Arab Emirates. pp.1-4 |
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hal-02088044v1
Communication dans un congrès
LiteX: an open-source SoC builder and library based on Migen Python DSL OSDA 2019, colocated with DATE 2019 Design Automation and Test in Europe, Mar 2019, Florence, Italy |
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hal-01936699v1
Communication dans un congrès
FFT Radix-2 and Radix-4 FPGA Acceleration Techniques Using HLS and HDL for Digital Communication Systems IEEE International Multidisciplinary Conference on Engineering Technology, (IMCET 2018), Nov 2018, Beirut, Lebanon |
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hal-03028409v1
Communication dans un congrès
Menhir: Generic High-Speed FPGA Model-Checker 2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.65-72, ⟨10.1109/DSD51259.2020.00022⟩ |
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hal-01326520v1
Communication dans un congrès
From Smalltalk to Silicon: Towards a methodology to turn Smalltalk code into FPGA IWST 14, Aug 2014, Cambridge, United Kingdom |
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hal-01179466v1
Communication dans un congrès
A Meta Model Supporting both Hardware and Smalltalk-based Execution of FPGA Circuits IWST 2015, ESUG, Jul 2015, Bressia, Italy. ⟨10.1145/2811237.2811296⟩ |
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hal-01406641v1
Communication dans un congrès
CaRDIN: An Agile Environment for EdgeComputing on Reconfigurable Sensor Networks 3rd IEEE International Conference on Computational Science and Computational Intelligence (CSCI 2016), Dec 2016, Las Vegas, United States |
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tel-02319236v1
Thèse
Du prototypage à l’exploitation d’overlays FPGA Systèmes embarqués. ENSTA Bretagne - École nationale supérieure de techniques avancées Bretagne, 2018. Français. ⟨NNT : 2018ENTA0003⟩ |
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hal-00989984v1
Communication dans un congrès
FPGAs virtuels : enjeux et usages COMPAS 2014, Apr 2014, Neuchâtel, Switzerland |
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hal-03127356v1
Communication dans un congrès
Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture 2020 28th European Signal Processing Conference (EUSIPCO), Jan 2021, Amsterdam, Netherlands. pp.2363-2367, ⟨10.23919/Eusipco47968.2020.9287770⟩ |
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hal-03085342v1
Communication dans un congrès
Benchmarking Quantized Neural Networks on FPGAs with FINN DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures, Feb 2021, Grenoble, France |
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hal-00747713v1
Communication dans un congrès
HLS-based Fast Design Space Exploration of ad hoc hardware accelerators: a key tool for MPSoC Synthesis on FPGA International Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2012, Germany |
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