JIT Compiler Security through Low-Cost RISC-V Extension

Quentin Ducasse (1, 2) , Pascal Cotret (2, 1) , Loïc Lagadec (2, 1)

1 Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools
2 ENSTA Bretagne - École Nationale Supérieure de Techniques Avancées Bretagne

Language Virtual Machines (VM) need to be extremely efficient and hence use complex engines such as a JIT compiler to speed up the usual bytecode interpretation loop. Their usage of low-level and security-critical tasks make them targets of choice. Enforcing low-cost fine-grained memory isolation has been an important research focus as a countermeasure to the most advanced JIT attacks. Memory isolation splits the components of an application with controlled communication and verified access to other resources. We present how custom instructions linked to hardware-enforced domain-checking could protect JIT code and data. We present incremental solutions and their corresponding custom instructions. The generated machine code and extended RISC-V Rocket come at a low-cost both in performance and intrusiveness.

Domaines: Cryptographie et sécurité [cs.CR]

Quentin Ducasse, Pascal Cotret, Loïc Lagadec. JIT Compiler Security through Low-Cost RISC-V Extension. 30th Reconfigurable Architectures Workshop, May 2023, St Petersburg (Florida), United States. ⟨hal-04031296⟩