Prototyping FPGA through overlays - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2021

Prototyping FPGA through overlays

(1, 2) , (1, 2) , (1, 3)
1
2
3

Résumé

EFPGAs give designers the flexibility to make changes at any point in the chip's life span, even in the customers' systems. Though, eFPGA are not efficient from an integration perspective, making proper dimensionning and tailoring mandatory. Unfortunately, designing an eFPGA is a complex and error-prone task. Even though automatic generation from high level models can produce correct-by-construction layouts, integration remains complex due to process variation. A key point is then to reduce the technology dependency.This paper presents the ELNATH project in which three implementations of the same architecture have been addressed: overlay, eFPGA, and 55 nm FPGA thanks to an open-source integrated tool flow that supports defining, implementing and programming reconfigurable architectures.
Fichier non déposé

Dates et versions

hal-03761788 , version 1 (26-08-2022)

Identifiants

Citer

Theotime Bollengier, Loïc Lagadec, Ciprian Teodorov. Prototyping FPGA through overlays. 2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.15-21, ⟨10.1109/RSP53691.2021.9806222⟩. ⟨hal-03761788⟩
12 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook Twitter LinkedIn More