%0 Conference Paper %F Oral %T Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis %+ Equipe Hardware ARchitectures and CAD tools (Lab-STICC_ARCAD) %+ École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne) %+ Politecnico di Milano [Milan] (POLIMI) %+ Université de Bretagne Sud (UBS) %A Badier, Hannah %A Pilato, Christian %A Le Lann, Jean-Christophe %A Coussy, Philippe %A Gogniat, Guy %< avec comité de lecture %B DATE'21 Design Automation and Test in Europe %C Grenoble (virtuel), France %8 2021-02-01 %D 2021 %Z Computer Science [cs]/Hardware Architecture [cs.AR]Conference papers %X The increasing design and manufacturing costs are leading to globalize the semiconductor supply chain. However, a malicious attacker can resell a stolen Intellectual Property (IP) core, demanding methods to identify a relationship between a given IP and a potentially fraudulent copy. We propose a method to protect IP cores created with highlevel synthesis (HLS): our method inserts a discrete birthmark in the HLS-generated designs that uses only intrinsic characteristics of the final RTL. The core of our process leverages the side effects of HLS due to specific source-code manipulations, although the method is HLS-tool agnostic. We propose two independent validation metrics, showing that our solution introduces minimal resource and delay overheads (< 6% and < 2%, respectively) and the accuracy in detecting illegal copies is above 96%. %G English %2 https://hal.science/hal-03228922/document %2 https://hal.science/hal-03228922/file/date21_birthmarking_camera_ready.pdf %L hal-03228922 %U https://hal.science/hal-03228922 %~ UNIV-BREST %~ INSTITUT-TELECOM %~ ENSTA-BRETAGNE %~ CNRS %~ UNIV-UBS %~ ENSTA-BRETAGNE-STIC %~ ENIB %~ LAB-STICC %~ INSTITUTS-TELECOM %~ LAB-STICC_UBS_2 %~ LAB-STICC_ARCAD %~ LAB-STICC_SHARP