@inproceedings{akkad:hal-03127356,
  TITLE = {{Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture}},
  AUTHOR = {Akkad, Ghattas and Mansour, Ali and Elhassan, Bachar and Inaty, Elie and Ayoubi, Rafic},
  URL = {https://hal-ensta-bretagne.archives-ouvertes.fr/hal-03127356},
  BOOKTITLE = {{2020 28th European Signal Processing Conference (EUSIPCO)}},
  ADDRESS = {Amsterdam, Netherlands},
  PUBLISHER = {{IEEE}},
  SERIES = {European Signal Processing Conference},
  VOLUME = {2021},
  PAGES = {2363-2367},
  YEAR = {2021},
  MONTH = Jan,
  DOI = {10.23919/Eusipco47968.2020.9287770},
  KEYWORDS = {Antennas ; Architecture ; Computational complexity ; Errors ; Field programmable gate arrays (FPGA) ; Integrated circuit design ; Parallel architectures ; Pipelines ; Signal receivers ; Least mean square algorithm ; Antenna array ; Adaptive beamforming},
  HAL_ID = {hal-03127356},
  HAL_VERSION = {v1},
}