%0 Conference Proceedings
%T A Cost-effective Approach for Efficient Time-sharing of Reconfigurable Architectures
%+ Pôle STIC_IDM
%+ Lab-STICC_ENSTAB_ CACS_MOCS
%+ Institut de Recherche Technologique b-com (IRT b-com)
%A Najem, Mohamad
%A Bollengier, Théotime
%A Le Lann, Jean-Christophe
%A Lagadec, Loïc
%< avec comité de lecture
%B FPGA4GPC'2017
%C Hambourg, Germany
%8 2017-05-09
%D 2017
%R 10.1109/FPGA4GPC.2017.8008959
%K resource allocation
%K reconfigurable architectures
%K field programmable gate arrays
%K scheduling
%K overlay networks
%Z Computer Science [cs]Conference papers
%X Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced: i) a snapshot register to monitor the execution at run-time, and ii) a pre-loading to minimize the reconfiguration time overhead. We also propose accurate cost models of all components of the scheduling scheme. The proposed approach is evaluated on the APF6-SP SoC+FPGA platform. A 90% of models' preciseness is achieved, and costs 300x less in reconfiguration time compared to the literature.
%G English
%L hal-01656613
%U https://hal.science/hal-01656613
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