A Cost-effective Approach for Efficient Time-sharing of Reconfigurable Architectures

Mohamad Najem (1, 2) , Théotime Bollengier (3) , Jean-Christophe Le Lann (2, 1) , Loïc Lagadec (2, 1)

1 Pôle STIC_IDM
2 Lab-STICC_ENSTAB_ CACS_MOCS
3 IRT b-com - Institut de Recherche Technologique b-com

Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced: i) a snapshot register to monitor the execution at run-time, and ii) a pre-loading to minimize the reconfiguration time overhead. We also propose accurate cost models of all components of the scheduling scheme. The proposed approach is evaluated on the APF6-SP SoC+FPGA platform. A 90% of models' preciseness is achieved, and costs 300x less in reconfiguration time compared to the literature.

Mots clés: resource allocation; reconfigurable architectures; field programmable gate arrays; scheduling; overlay networks

Domaines: Informatique [cs]

Mohamad Najem, Théotime Bollengier, Jean-Christophe Le Lann, Loïc Lagadec. A Cost-effective Approach for Efficient Time-sharing of Reconfigurable Architectures. FPGA4GPC'2017, May 2017, Hambourg, Germany. ⟨10.1109/FPGA4GPC.2017.8008959⟩. ⟨hal-01656613⟩