S. Jayakumar and S. Sumathi, High speed vedic multiplier for image processing using FPGA, 2016 10th International Conference on Intelligent Systems and Control (ISCO), pp.1-4, 2016.
DOI : 10.1109/ISCO.2016.7727059

G. Bieszczad, SoC-FPGA embedded system for real-time thermal image processing, 2016 MIXDES, 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp.2016-469, 2016.
DOI : 10.1109/MIXDES.2016.7529788

Y. Toyoda, N. Koike, and Y. Li, An FPGA-based remote laboratory: Implementing semi-automatic experiments in the hybrid cloud, 2016 13th International Conference on Remote Engineering and Virtual Instrumentation (REV), pp.24-29, 2016.
DOI : 10.1109/REV.2016.7444435

S. A. Fahmy, K. Vipin, and S. Shreejith, Virtualized FPGA Accelerators for Efficient Cloud Computing, 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom), pp.2015-430
DOI : 10.1109/CloudCom.2015.60

URL : http://wrap.warwick.ac.uk/74757/7/WRAP_cloudcom2015-fahmy.pdf

F. Chen, Y. Shan, Y. Zhang, Y. Wang, H. Franke et al., Enabling FPGAs in the cloud, Proceedings of the 11th ACM Conference on Computing Frontiers, CF '14, pp.1-310
DOI : 10.1145/2597917.2597929

W. Wang, M. Bolic, and J. Parri, pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp.1-9
DOI : 10.1109/CODES-ISSS.2013.6658997

R. Brodersen, A. Tkachenko, and H. K. So, A unified hardware/software runtime environment for fpga-based reconfigurable computers using borph, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), pp.259-264, 2006.

R. Kirchgessner, G. Stitt, A. George, and H. Lam, VirtualRC, Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA '12, pp.205-208
DOI : 10.1145/2145694.2145728

J. D. Dondo, J. Barba, F. Rincn, F. Moya, and J. C. Lpez, Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs, Journal of Systems Architecture, vol.59, issue.1, pp.1-15, 2013.
DOI : 10.1016/j.sysarc.2012.09.001

S. Byma, J. G. Steffan, H. Bannazadeh, A. L. Garcia, and P. Chow, FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, pp.2014-109, 2014.
DOI : 10.1109/FCCM.2014.42

O. Knodel and R. G. Spallek, Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud, 2015 Euromicro Conference on Digital System Design, pp.2015-337, 2015.
DOI : 10.1109/DSD.2015.37

M. Feilen, M. Ihmig, C. Schwarzbauer, and W. Stechele, Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources, 22nd International Conference on Field Programmable Logic and Applications (FPL), pp.75-82, 2012.
DOI : 10.1109/FPL.2012.6339244

B. Ronak and S. A. Fahmy, Improved resource sharing for FPGA DSP blocks, 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp.1-4, 2016.
DOI : 10.1109/FPL.2016.7577373

A. Bourge, O. Muller, and F. Rousseau, Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, pp.2015-155, 2015.
DOI : 10.1109/FCCM.2015.8

URL : https://hal.archives-ouvertes.fr/hal-01164923

F. Duhem, F. Muller, and P. Lorenzini, Reconfiguration time overhead on field programmable gate arrays: reduction and cost model, IET Computers & Digital Techniques, vol.6, issue.2
DOI : 10.1049/iet-cdt.2011.0033

A. K. Jain, D. L. Maskell, and S. A. Fahmy, Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?, 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech), pp.586-593, 2016.
DOI : 10.1109/DASC-PICom-DataCom-CyberSciTec.2016.110

A. Brant and G. Lemieux, ZUMA: An Open FPGA Overlay Architecture, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp.2012-93, 2012.
DOI : 10.1109/FCCM.2012.25

URL : http://www.ece.ubc.ca/~lemieux/publications/brant-fccm2012.pdf

A. K. Jain, X. Li, P. Singhai, D. L. Maskell, and S. A. Fahmy, DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.1-8, 2016.
DOI : 10.1109/FCCM.2016.10

D. Koch, C. Beckhoff, and G. G. Lemieux, An efficient FPGA overlay for portable custom instruction set extensions, 2013 23rd International Conference on Field programmable Logic and Applications, pp.2013-2014, 2013.
DOI : 10.1109/FPL.2013.6645517

URL : http://www.ece.ubc.ca/~lemieux/publications/koch-fpl2013.pdf

R. Lysecky, K. Miller, F. Vahid, and K. , Vissers, Firm-core virtual fpga for just-intime fpga compilation (abstract only, Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays FPGA '05, pp.271-281, 2005.
DOI : 10.1145/1046192.1046247

T. Wiersema, A. Bockhorn, and M. Platzner, Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), pp.1-6, 2014.
DOI : 10.1109/ReConFig.2014.7032514

V. Betz and J. Rose, VPR: a new packing, placement and routing tool for FPGA research, International Workshop on Field Programmable Logic and Applications, pp.213-222, 1997.
DOI : 10.1007/3-540-63465-7_226

URL : http://www.eecg.toronto.edu/~vaughn/papers/fpl97.pdf

G. Stitt and J. Coole, Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation, IEEE Embedded Systems Letters, vol.3, issue.3, pp.81-84, 2011.
DOI : 10.1109/LES.2011.2167713

D. Capalija and T. S. Abdelrahman, A high-performance overlay architecture for pipelined execution of data flow graphs, 2013 23rd International Conference on Field programmable Logic and Applications, pp.1-8, 2013.
DOI : 10.1109/FPL.2013.6645515

J. Benson, R. Cofell, C. Frericks, C. H. Ho, V. Govindaraju et al., Sankaralingam , Design, integration and implementation of the dyser hardware accelerator into opensparc, IEEE International Symposium on High-Performance Comp Architecture, pp.1-12, 2012.

C. Liu, H. C. Ng, and H. K. So, QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay, 2015 International Conference on Field Programmable Technology (FPT), pp.56-63, 2015.
DOI : 10.1109/FPT.2015.7393130

L. Lagadec, J. Le-lann, and T. Bollengier, A prototyping platform for virtual reconfigurable units, 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp.2014-2015, 2014.
DOI : 10.1109/ReCoSoC.2014.6860689

URL : https://hal.archives-ouvertes.fr/hal-01006128

K. Jozwik, H. Tomiyama, M. Edahiro, S. Honda, and H. Takada, Comparison of Preemption Schemes for Partially Reconfigurable FPGAs, IEEE Embedded Systems Letters, vol.4, issue.2, pp.45-48, 2012.
DOI : 10.1109/LES.2012.2193660

T. Bollengier, L. Lagadec, M. Najem, J. Le-lann, and P. Guilloux, Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach, pp.93-105
DOI : 10.1063/1.1697872

URL : https://hal.archives-ouvertes.fr/hal-01475251

A. Zarrabi, A Generic Process Migration Algorithm, International Journal of Distributed and Parallel systems, vol.3, issue.5, 2012.
DOI : 10.5121/ijdps.2012.3504

T. Bollengier, M. Najem, J. C. Lann, and L. Lagadec, Demo: Overlay architectures for heterogeneous FPGA cluster management, 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.2016-239
DOI : 10.1109/DASIP.2016.7853832