%0 Conference Proceedings
%T Soft timing closure for soft programmable logic cores: The ARGen approach
%+ Institut de Recherche Technologique b-com (IRT b-com)
%+ Lab-STICC_ENSTAB_ CACS_MOCS
%+ Pôle STIC_IDM
%+ Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN)
%A Bollengier, Théotime
%A Lagadec, Loïc
%A Najem, Mohamad
%A Le Lann, Jean-Christophe
%A Guilloux, Pierre
%< avec comité de lecture
%B ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing
%C Delft, Netherlands
%8 2017-04-03
%D 2017
%K Reconfigurable cores
%Z Computer Science [cs]/Hardware Architecture [cs.AR]Conference papers
%X Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flip-flops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores.
%G English
%2 https://hal.science/hal-01475251/document
%2 https://hal.science/hal-01475251/file/paper_6-4.pdf
%L hal-01475251
%U https://hal.science/hal-01475251
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