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A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators

Mohamed Ben Hammouda 1 Philippe Coussy 2 Loïc Lagadec 3, 4
1 Lab-STICC_UBO_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance, UBO - Université de Brest
2 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 Lab-STICC_ENSTAB_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
4 Pôle STIC_IDM
ENSTA Bretagne - École Nationale Supérieure de Techniques Avancées Bretagne
Abstract : Security and safety are more and more important in embedded system design. A key issue hence lies in the ability of systems to respond safely when errors occur at runtime, to prevent unacceptable behaviors that can lead to failures or sensitive data leakage. In this paper, we propose a design approach that automatically generates On-Chip Monitors (OCM) during High- Level Synthesis (HLS) of hardware accelerators (HWacc). OCM checks at runtime the input/output timing behavior, the control flow execution and algorithmic properties (via ANSI-C assertions) of the monitored HWacc. OCM is implemented separately from the HWacc and an original technique is introduced for their synchronization. Two synthesis options are proposed to tradeoff between performance and area. Experiment results show that error detection on the control flow is 16x better compared to the existing approaches while the cost of assertions is reduced by 17.48% on average. The impact on execution time (i.e. latency of the HWacc) is decreased by 2.76x at no area penalty and up to 4.5x with less than 10% extra-area. The clock period overhead is at worst less than 5% and the overhead on the synthesis time of the HWacc to generate OCMs is 7.44% on average.
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https://hal.archives-ouvertes.fr/hal-01405531
Contributeur : Annick Billon-Coat <>
Soumis le : mercredi 30 novembre 2016 - 10:26:04
Dernière modification le : mercredi 24 juin 2020 - 16:19:30

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Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec. A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36 (3), pp.384-397. ⟨10.1109/TCAD.2016.2587278⟩. ⟨hal-01405531⟩

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