%0 Conference Proceedings
%T From Smalltalk to Silicon: Towards a methodology to turn Smalltalk code into FPGA
%+ Lab-STICC_ENSTAB_CACS_MOCS
%+ Centre for Digital Systems (CERI SN - IMT Nord Europe)
%A Sang, Le Xuan
%A Lagadec, Loïc
%A Fabresse, Luc
%A Laval, Jannik
%A Bouraqadi, Noury
%< avec comité de lecture
%B IWST 14
%C Cambridge, United Kingdom
%8 2014-08-18
%D 2014
%K Smalltalk
%K Dynamic Reflective Language.
%K Pharo
%K FPGA
%K VHDL
%K Native Boost
%K robotic
%K Dynamic Reflective Language
%Z Computer Science [cs]/Symbolic Computation [cs.SC]
%Z Computer Science [cs]/Software Engineering [cs.SE]
%Z Computer Science [cs]/Mobile Computing
%Z Computer Science [cs]/Computation and Language [cs.CL]Conference papers
%X Due to their ability to combine high performances along with flexibility, FPGAs (Field Programmable Gate Array) are used in robotic applications nowadays, especially in case of realtime applications. The FPGA circuits are often designed and configured using the Hardware Description Languages (HDLs) like VHDL or Verilog. However, although these languages provide abstractions up to the functionality level, they lack many features of todays modern languages that make them unsuited for high-level models and systems. In this paper, we present an overview of a methodology that uses a Dynamic Reflective Language, such as Smalltalk, for high level hardware/software co-design on FPGAs.
%G English
%2 https://hal.science/hal-01326520/document
%2 https://hal.science/hal-01326520/file/from%20smalltalk%20to%20silicon.pdf
%L hal-01326520
%U https://hal.science/hal-01326520
%~ UNIV-BREST
%~ INSTITUT-TELECOM
%~ ENSTA-BRETAGNE
%~ CNRS
%~ UNIV-UBS
%~ ENSTA-BRETAGNE-STIC
%~ LAB-STICC
%~ INSTITUTS-TELECOM
%~ IMT-NORD-EUROPE
%~ CERI-SN