A Formal, Model-driven Design Flow for System Simulation and Multi-core Implementation
Résumé
With the growing complexity of Real-Time Embedded Systems (RTES),
there is a huge interest in using modeling languages such as the Unified
Modeling Language (UML), and other Model-Driven Engineering (MDE)
techniques targeting RTES system design. These approaches provide
language abstractions for system design, allowing to focus on
their relevant properties. Unfortunately, such approaches still suffer
from several shortcomings including the lack of well-defined semantics.
Therefore, it remains difficult to connect the MDE specification tools
and the design tools that are based on formal grounds and well-defined
semantics to perform analysis, validation or system synthesis for RTES.
This paper presents a top-down RTES design flow aiming to reduce
the gap between MDE and formal design approaches. We present the
connection between a framework dedicated to the enrichment of modeling
languages such as UML with formal semantics, a framework based on formal
models of computation supporting validation by simulation, and a system
synthesis tool targeting a flexible platform with well-defined execution
services. Our purpose is to cover several system design phases from
specification, simulation down to implementation on a platform. As a
case study, a JPEG Encoder application was realized following the
different design steps of the tool-chain.