%0 Conference Proceedings %T Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGA %+ Institut d'Électronique et des Technologies du numéRique (IETR) %+ Lab-STICC_ENSTAB_CACS_MOCS %+ Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) %A Basheer Ahmed, Chagun Basha %A Pillement, Sébastien %A Lagadec, Loïc %A Tisserand, Arnaud %< avec comité de lecture %B Conférence d’informatique en Parallélisme, Architecture et Système (Compas) %C Villeneuve d'Ascq, France %P 10 %8 2015-06-30 %D 2015 %Z Engineering Sciences [physics]Conference papers %X Virtual prototyping supports fast exploration of design space for new embedded platforms.Uses of FPGA in critic environment requires to design adapted circuits at the cheapest costpossible. We then aim at developing a low-cost fault-tolerant FPGA. This work relies on a modulardesign flow and embedding custom logic units ranging from medium-to-coarse grained(e.g. arithmetic units, with dedicated encoding in order to address fault detection). The reconfigurableunit is modelled in a high level framework that outputs VHDL files to be later takenas input by commercial framework for implementation. As so, our prototyping environmentsupports both virtual prototype simulation and hardware emulation. Besides, it provides a baselinefor manual refinement or modular replacement when going to silicon. %G English %L hal-01153568 %U https://hal.science/hal-01153568 %~ UNIV-BREST %~ UNIV-NANTES %~ INSTITUT-TELECOM %~ ENSTA-BRETAGNE %~ UNIV-RENNES1 %~ CNRS %~ INRIA %~ UNIV-UBS %~ INSA-RENNES %~ INRIA-RENNES %~ IRISA %~ IETR %~ ENSTA-BRETAGNE-STIC %~ IRISA_SET %~ INRIA_TEST %~ IETR_SCN %~ TESTALAIN1 %~ LAB-STICC %~ CENTRALESUPELEC %~ IRISA-D3 %~ INRIA2 %~ UR1-HAL %~ UR1-MATH-STIC %~ UR1-UFR-ISTIC %~ IETR-SYSCOM %~ IETR-SC %~ TEST-UNIV-RENNES %~ TEST-UR-CSS %~ UNIV-RENNES %~ INRIA-RENGRE %~ INSA-GROUPE %~ INSTITUTS-TELECOM %~ ANR %~ UR1-MATH-NUM %~ IETR-ASIC %~ NANTES-UNIVERSITE %~ UNIV-NANTES-AV2022 %~ IETR-NANTES