Hardware-Software Co-Design for Security: ECC Processor Example

Arnaud Tisserand (1)

1 Lab-STICC_UBS_CACS_MOCS

Designing accelerators or blocks for security and cryptography in hardware usually leads to mode efficient and secure solutions than pure software implementations. But this can also lead to a flexibility problem: e.g. limited updates and adaptation to various security levels. We will present some ideas and results on the design of cryptoprocessors mixing hardware efficiency (speed, energy and security) and software flexibility in the case of elliptic curve cryptography for embedded systems.

Domaines: Architectures Matérielles [cs.AR]; Arithmétique des ordinateurs; Cryptographie et sécurité [cs.CR]; Micro et nanotechnologies/Microélectronique

Arnaud Tisserand. Hardware-Software Co-Design for Security: ECC Processor Example. Workshop on the Security of Software / Hardware Interfaces, Nov 2019, Rennes, France. ⟨hal-02374396⟩