Area time power estimation for FPGA based designs at a behavioral level

Sébastien Bilavarn (1) , Guy Gogniat (2) , Jean-Luc Philippe (3)

1 LEAT - Laboratoire d'Electronique, Antennes et Télécommunications
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 Lab-STICC_UBS_CACS_MOCS

A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification.

Mots clés: formal specification; resource allocation; area time power estimation; FPGA based designs; behavioral level; performance estimation technique; power consumption estimation; behavioral specification; Field programmable gate arrays; High level synthesis; Design methodology; Space technology; Bismuth; Testing; Array signal processing; Signal processing algorithms; Process design; Time factors

Domaines: Systèmes embarqués

Sébastien Bilavarn, Guy Gogniat, Jean-Luc Philippe. Area time power estimation for FPGA based designs at a behavioral level. IEEE International Conference on Electronics, Circuits and Systems, 2000, Beirut, Lebanon. ⟨10.1109/ICECS.2000.911593⟩. ⟨hal-01017471⟩