Power Estimation of a C algorithm based on the Functional- Level Power Analysis of a Digital Signal Processor

Nathalie Julien (1) , Johann Laurent , Eric Senn (1) , Eric Martin (1)

1 Lab-STICC_UBS_CACS_MOCS

A complete methodology to estimate power consumption at the C-level for on-the-shelf processors is introduced. It relies on the Functional-Level Power Analysis, which results in a power model of the processor that describes the consumption variations relatively to algorithmic and configuration parameters. Some parameters can be predicted directly from the C-algorithm with simple assumptions on the compilation. Maximum and minimum bounds for power consumption are obtained, together with a very accurate estimation; for the TI C6x, a maximum error of 6% against measurements is obtained for classical digital signal processing algorithms. Estimation results are summarized on a consumption map; the designer can compare the algorithm consumption, and its variations, with the application constraints.

Mots clés: Power Estimation; DSP; C code; Energy; Characterization

Domaines: Architectures Matérielles [cs.AR]

Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin. Power Estimation of a C algorithm based on the Functional- Level Power Analysis of a Digital Signal Processor. 2002, pp 354-360. ⟨hal-00077553⟩