A Memory Aware High Level Synthesis Tool

Gwenolé Corre (1) , Nathalie Julien (2) , Eric Senn (2) , Eric Martin (2)

1 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
2 Lab-STICC_UBS_CACS_MOCS

We introduce a new approach to take into account the memory architecture and the memory mapping in High- Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

Mots clés: HLS Tool; memory constraint

Domaines: Architectures Matérielles [cs.AR]

Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin. A Memory Aware High Level Synthesis Tool. International Symposium on VLSI, 2004, Lafayette, Louisiana, United States. pp.279-280. ⟨hal-00077377⟩